1. Field of the Invention
Example embodiments of the present invention relate generally to a timing generator and methods thereof, and more particularly to a timing generator and methods of generating a timing control signal.
2. Description of the Related Art
Conventional mobile communication systems (e.g., mobile phones, personal communication services (PCS), and personal digital assistants (PDAs), etc.) may be configured to support wireless communications.
FIG. 1 is a block diagram illustrating a conventional wireless digital transceiver. Referring to FIG. 1, the conventional wireless digital transceiver may include an antenna 50, a radio frequency (RF) processing unit 10, an analog baseband processing unit 30 and a digital baseband processing unit 40. The wireless digital transceiver of FIG. 1 may employ an intermediate frequency (IF) (e.g., within a superheterodyne wireless digital transceiver). The conventional wireless digital transceiver of FIG. 1 may further include an intermediate frequency (IF) processing unit 20 positioned between the RF processing unit 10 and the analog baseband processing unit 30.
Referring to FIG. 1, the RF processing unit 10 may demodulate an RF signal received from the antenna 50 in a receiving operation, and may convert the received RF signal into a baseband signal. In a transmitting operation, the RF processing unit 10 may modulate the baseband signal or an IF signal supplied from a host device and may transmit the modulated signal to the antenna 50.
Referring to FIG. 1, the intermediate frequency processing unit 20 may convert an IF signal into a baseband signal during a receiving operation, and may convert a baseband signal into an IF signal during a transmitting operation. During the receiving operation, the analog baseband processing unit 30 may convert the received analog baseband signal into a digital signal through an analog-to-digital conversion, and may further convert a sampling rate thereof to transmit the converted signal to the digital baseband processing unit 40. During the transmitting operation, the analog baseband processing unit 30 may convert the sampling rate of the received digital signal, and may further convert the received digital signal into an analog baseband signal through a digital-to analog conversion and may output the analog baseband signal.
Referring to FIG. 1, the digital baseband processing unit 40 may perform a channel decoding of the digital signal transmitted from the analog baseband processing unit 30 during the receiving operation, and may perform a channel coding (e.g., encoding) during the transmitting operation.
Referring to FIG. 1, each of the elements 10 through 40 may be implemented as integrated chips. For example, the RF processing unit 10 may be implemented in a RF transceiver chip, the analog baseband processing unit 30 may be implemented in an analog baseband chip, etc. Accordingly, an analog baseband chip may be configured to be compatible with numerous types of RF transceiver chips.
A conventional analog baseband chip may include a timing generator, which may alternatively be referred to as a timing generation unit (TGU). The timing generator may synchronize a control word for controlling an analog in-phase/quadrature (I/Q) signal to be transmitted to the RF transceiver chip with an internally generated clock signal, and may output the synchronized control word.
A clock signal used to output the control word may be synchronized with an operating clock signal of the external RF transceiver chip to allow the timing generator to cooperate with the RF transceiver chip. Accordingly, the timing generator may be configured to support the delay resolution of the clock signals of the RF transceiver chips so as to be adaptable to a variety of operating clock signals among different RF transceiver chips.
The delay resolution may represent a signal precision level for identifying a delay of the clock signal. Conceptually, delay resolution may be similar to image resolution. The delay resolution may be proportional to a frequency of the clock signal and inversely proportional to a period of the clock signal. For example, higher delay resolutions may be associated with higher frequencies and lower unit cycles (i.e., clock cycles) in corresponding clock signals. Likewise, lower delay resolutions may be associated with lower frequencies and higher unit cycles in corresponding clock signals.
However, because conventional timing generators may output the control word to a transceiver chip based upon an internally generated base clock signal, it may be difficult to configure a conventional timing generator to support different types of clock signals (e.g., because such signals may be generated “external” to the timing generator).
FIG. 2 is a block diagram illustrating a conventional timing generator 60 and a digital baseband chip 70. The timing generator 60 may form a portion of an analog baseband chip (not shown).
Referring to FIG. 2, the timing generator 60 may include a clock generator 61, a random-access memory (RAM) 64, a duration counter 62 and a control word output register 63. The clock generator 61 may generate a base clock signal for outputting a control word and for controlling respective units of the timing generator 60. The RAM 64 may be connected to the external digital baseband chip 70. The RAM 64 may store information received from the digital baseband chip 70. The stored information may include, for example, a plurality of control word identifications (IDs), addresses of a number of control words, and clock cycles for controlling output timings of the respective control words.
Referring to FIG. 2, the duration counter 62 may receive, from the RAM 64, clock cycle information for controlling an output of the respective control words. The duration counter 62 may synchronize with (e.g., count clock cycles of) a base clock signal based on the received clock cycle information. Accordingly, a control word may be outputted during a duration period, which may be counted by the duration counter 62, based on received clock cycle information.
Referring to FIG. 2, the control word output register 63 may receive the control word transferred from the RAM 64 and may output the transferred control word during the duration time counted by the duration counter 62, such that the control word may be supplied to an external RF transceiver chip (not shown).
As described above, the timing generator 60 may output the control word for controlling a timing of an analog (I/Q) signal during a fixed clock cycle, which may be designated by the digital baseband chip 70, according to the base clock signal generated by the clock generator 61.
However, conventional timing generators may not be configured to adapt to RF transceiver chips having different delay resolutions, because the outputted control words may only be capable of being synchronized with the base clock signal, which may be generated internally at the timing generator (e.g., as shown in FIG. 2). In other words, a conventional timing generator may only be capable of operation with an RF transceiver chip having a particular delay resolution.
For example, if a unit cycle (e.g., clock cycle or period) of the base clock signal generated in the timing generator is a ⅛ symbol clock and a unit cycle of the RF transceiver chip for transferring the control word is a 1/24 symbol clock, the timing generator may not support an optimal operation speed of the RF transceiver chip because the delay resolution of the operation clock for the RF transceiver chip may be three times higher than that of the base clock signal for the clock generator. Thus, in order to synch the timing generator with the RF transceiver chip, the base clock signal at the timing generator may be redesigned so as to correspond with an operation clock signal of the RF transceiver chip. Such a redesign process is a laborious, time-consuming and expensive process.